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DISCRETE SEMICONDUCTORS
DATA SHEET
andbook, halfpage
MBD128
BF1205 Dual N-channel dual gate MOS-FET
Product specification 2003 Sep 30
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
FEATURES * Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias * Internal switch reduces the number of external components * Superior cross-modulation performance during AGC * High forward transfer admittance * High forward transfer admittance to input capacitance ratio. APPLICATIONS * Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage, such as digital and analog television tuners and professional communications equipment. DESCRIPTION The BF1205 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME BF1205 - DESCRIPTION Plastic surface mounted package; 6 leads
1 2 Top view 3 g1 (a) g2
handbook, halfpage
BF1205
PINNING - SOT363 PIN 1 2 3 4 5 6 gate 1 (a) gate 2 gate 1 (b) drain (b) source drain (a) DESCRIPTION
d (a) 4
s
d (b)
6
5
AMP a
AMP b
g1 (b)
MGX429
Marking code: L4-.
Fig.1 Simplified outline and symbol.
VERSION SOT363
2003 Sep 30
2
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS
BF1205
MIN. TYP. MAX. UNIT - - - - - 31 1.8 2.0 20 1.2 1.4 102 105 -
Per MOS-FET; unless otherwise specified VDS ID Ptot yfs Cig1-ss Crss NF Xmod drain-source voltage drain current (DC) total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation Ts 102 C; temperature at the soldering point of the source lead ID = 12 mA amp. a: f = 1 MHz amp. b: f = 1 MHz f = 1 MHz amp. a: f = 800 MHz amp. b: f = 800 MHz amp. a: input level for k = 1% at 40 dB AGC amp. b: input level for k = 1% at 40 dB AGC Tj junction temperature CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS - - - - Ts 102 C; note - -65 - MIN. MAX. UNIT 10 30 200 40 2.3 2.5 - 1.9 2.1 - - 150 V mA mW mS pF pF fF dB dB dBV dBV C
- 26 - - - - - 98 100 -
Per MOS-FET; unless otherwise specified VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Ts is the temperature at the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 240 UNIT K/W drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation storage temperature junction temperature 10 30 10 10 200 +150 150 V mA mA mA mW C C
2003 Sep 30
3
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
250 Ptot 200
MGS359
(mW)
150
100
50
0 0 50 100 150 Ts (C) 200
Fig.2 Power derating curve.
STATIC CHARACTERISTICS Tj = 25 C; per MOS-FET; unless otherwise specified. SYMBOL V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX PARAMETER drain-source breakdown voltage gate-source breakdown voltage gate-source breakdown voltage forward source-gate voltage forward source-gate voltage gate-source threshold voltage gate-source threshold voltage drain-source current CONDITIONS MIN. MAX. - - 10 10 1.5 1.5 1 1.0 16 16 50 50 20 UNIT V V V V V V V V mA mA nA nA nA amp. a: VG1-S = VG2-S = 0 V; ID = 10 A 10 amp. b: VG1-S = VG2-S = 0 V; ID = 10 A 7 VGS = VDS = 0 V; IG1-S = 10 mA VGS = VDS = 0 V; IG2-S = 10 mA VG2-S = VDS = 0 V; IS-G1 = 10 mA VG1-S = VDS = 0 V; IS-G2 = 10 mA VDS = 5 V; VG2-S = 4 V; ID = 100 A VDS = 5 V; VG1-S = 5 V; ID = 100 A amp. a: VG2-S = 4 V; VDS = 5 V; RG1 = 150 k; note 1 amp. b: VG2-S = 4 V; VDS = 5 V; RG1 = 150 k; note 2 IG1-S IG2-S Note 1. RG1 connects gate 1 (b) to VGG = 0 V (see Fig.4). 2. RG1 connects gate 1 (b) to VGG = 5 V (see Fig.4). gate cut-off current gate cut-off current amp. a: VG1-S = 5 V; VG2-S = VDS = 0 V amp. b: VG1-S = 5 V; VG2-S = VDS = 0 V VG2-S = 4 V; VG1-S = VDS = 0 V 6 6 0.5 0.5 0.3 0.4 8 8 - - -
2003 Sep 30
4
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
16
MGX430
ID (mA) 12
(1)
handbook, halfpage
(2)
g1 (a) g2
d (a) s d (b) R G1
(3)
8
g1 (b)
4
(4) (5) (6)
VGG
MGX431
0 0 1 2 3 4 VGG (V) 5
(1) ID (b); RG1 = 120 k. (2) ID (b); RG1 = 150 k. (3) ID (b); RG1 = 180 k.
(4) ID (a); RG1 = 180 k. (5) ID (a); RG1 = 150 k. (6) ID (a); RG1 = 120 k.
VGG = 5 V: amplifier a is OFF; amplifier b is ON. VGG = 0 V: amplifier a is ON; amplifier b is OFF.
Fig.3 Drain currents of MOS-FET a and b as functions of VGG (see Fig.4).
Fig.4 Functional diagram
2003 Sep 30
5
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
DYNAMIC CHARACTERISTICS AMPLIFIER a Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; note 1 SYMBOL yfs Cig1-ss Cig2-ss Coss Crss Gtr PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance power gain Tj = 25 C f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BS(opt); GL = 0.5 mS; BL = BL(opt) f = 400 MHz; GS = 2 mS; BS = BS(opt); GL = 1 mS; BL = BL(opt) CONDITIONS MIN. 26 - - - - 31 27 TYP. 31 1.8 3.3 0.75 20 35 31 26 4 1.1 1.2 - 90 102
BF1205
MAX. 40 2.3 - - - 39 35 30 - 1.7 1.9 - - -
UNIT mS pF pF pF fF dB dB dB dB dB dB dBV dBV dBV
f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 22 GL = 1 mS; BL = BL(opt) NF noise figure f = 10.7 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS(opt) f = 800 MHz; YS = YS(opt) Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 10 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 Notes 1. For the MOS-FET not in use: VG1-S (b) = 0 V; VDS (b) = 0 V. 2. Measured in Fig.13 test circuit. - - - 90 - 98
2003 Sep 30
6
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
GRAPHS FOR AMPLIFIER a
BF1205
handbook, halfpage
20
MGX432
ID (mA) 15
(3) (2) (1)
(4)
handbook, halfpage
(5)
24
MGX433
ID (mA) 16
(6)
(1)
(2)
(3) (4) (5) (6)
10
8 5
(7)
(7)
0 0 0.4 0.8 1.2 2 1.6 VG1-S (V)
0 0 2 4 6 8 10 VDS (V)
(1) (2) (3) (4)
VG2-S = 4 V. VG2-S = 3.5 V. VG2-S = 3 V. VG2-S = 2.5 V.
(5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V.
(1) (2) (3) (4)
VG1-S (a) = 1.4 V. VG1-S (a) = 1.3 V. VG1-S (a) = 1.2 V. VG1-S (a) = 1.1 V.
(5) VG1-S (a) = 1 V. (6) VG1-S (a) = 0.9 V. (7) VG1-S (a) = 0.8 V.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
VG2-S = 4 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
Fig.5
Transfer characteristics; typical values; amplifier a.
Fig.6
Output characteristics; typical values; amplifier a.
2003 Sep 30
7
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
40
MGX434
handbook, halfpage
(1) (2)
12
MGX435
yfs (mS) 30
ID (a) (mA)
(3) (4)
8
20
4 10
(5)
0 0 4 8 12 16 20 ID (mA)
0 0 10 20 30 40 ID (b) (A)
(1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V.
(4) VG2-S = 2.5 V. (5) VG2-S = 2 V. VDS (a) = 5 V; VG2-S = 4 V; VDS (b) = 5 V; VG1-S (b) = 0 V; Tj = 25 C.
VDS (a) = 5 V; VG1-S (b) = VDS (b) = 0 V; Tj = 25 C.
Fig.8 Fig.7 Forward transfer admittance as a function of drain current; typical values; amplifier a.
Drain current as a function of internal G1 current (current in pin drain (b) if MOS-FET (b) is switched off); typical values; amplifier a.
2003 Sep 30
8
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage I
12
MGX436
D (mA) 10
(1)
(2) (3) (4)
handbook, halfpage
120
MGX437
Vunw (dBV) 110
8
(5)
6
100
4 90 2
0 0 2 4 6 VGG = VDS (V)
80 0 20 40 60 gain reduction (dB)
(1) VDS (b) = 5 V. (2) VDS (b) = 4.5 V. (3) VDS (b) = 4 V.
(4) VDS (b) = 3.5 V. (5) VDS (b) = 3 V.
VDS (a) = 5 V; VG1-S (b) = 0 V; Gate 1 (a) = open; Tj = 25 C.
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f w = 50 MHz; f unw = 60 MHz; Tamb = 25 C; see Fig.13.
Fig.9
Drain current as a function of gate 2 and drain supply voltage; typical values; amplifier a.
Fig.10 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier a.
2003 Sep 30
9
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
0
MGX438
handbook, halfpage
16
MGX439
gain reduction (dB) 20
ID (mA) 12
8
40 4
60 0 1 2 3 VAGC (V) 4
0 0 20 40 60 gain reduction (dB)
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; see Fig.13.
VDS (a) = VDS (b) = 5 V; VG1-S (b) = 0 V; f = 50 MHz; Tamb = 25 C; see Fig.13.
Fig.11 Gain reduction as a function of AGC voltage; typical values; amplifier a.
Fig.12 Drain current as a function of gain reduction; typical values; amplifier a.
handbook, full pagewidth
VAGC
VDS(a) 5V 4.7 nF
10 k 4.7 nF RGEN 50 Vi 50 4.7 nF g1 (a) d (a)
L1 2.2 H 4.7 nF RL 50
g2
BF1205
s
4.7 nF 50
g1 (b)
d (b) L2 2.2 H
R G1 150 k
4.7 nF VGG 0V VDS(b) 5V
MGX440
Fig.13 Cross-modulation test set-up for amplifier a.
2003 Sep 30
10
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
102 handbook, halfpage yis (mS) 10 b is 1
MGX441
102 handbook, halfpage
MGX442
-102
| yfs | (mS) | yfs |
fs (deg)
10
-10
10-1
g is
fs
10-2 10
102
f (MHz)
103
1 10
102
f (MHz)
-1 103
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA.
Fig.14 Input admittance as a function of frequency; typical values; amplifier a.
Fig.15 Forward transfer admittance and phase as a function of frequency; typical values; amplifier a.
103 handbook, halfpage
MGX443
-103 rs (deg)
MGX444
handbook, halfpage
10
| yrs|
(S) 102 rs
yos (mS) 1 bos
-102
10
| yrs|
-10
10-1
gos
1 10
102
f (MHz)
-1 103
10-2 10
102
f (MHz)
103
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA.
VDS (a) = 5 V; VG2-S (a) = 4 V; VDS (b) = VG1-S (b) = 0 V; ID (a) = 12 mA.
Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier a.
Fig.17 Output admittance as a function of frequency; typical values; amplifier a.
2003 Sep 30
11
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
Scattering parameters: amplifier a VDS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 C f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 s11 MAGNITUDE (ratio) 0.997 0.995 0.988 0.976 0.963 0.944 0.924 0.900 0.874 0.846 0.817 ANGLE (deg) -3.70 -7.37 -14.64 -21.85 -28.95 -35.98 -42.90 -49.77 -56.61 -63.18 -69.84 s21 MAGNITUDE (ratio) 3.15 3.15 3.12 3.09 3.04 2.99 2.94 2.87 2.81 2.73 2.65 ANGLE (deg) 175.99 171.92 163.99 156.06 148.32 140.52 132.88 125.30 117.79 110.29 102.91 s12 MAGNITUDE (ratio) 0.00067 0.00132 0.00262 0.00373 0.00471 0.00557 0.00624 0.00669 0.00701 0.00705 0.00688 ANGLE (deg) 86.39 84.34 79.71 75.29 71.43 66.89 63.52 60.09 59.58 52.42 49.17
BF1205
s22 MAGNITUDE (ratio) 0.992 0.991 0.990 0.988 0.985 0.982 0.978 0.975 0.972 0.968 0.965 ANGLE (deg) -1.38 -2.83 -5.62 -8.40 -11.15 -13.88 -16.65 -19.35 -22.08 -24.87 -27.63
Noise data VDS (a) = 5 V; VG2-S = 4 V; ID (a) = 12 mA; VDS (b) = 0 V; VG-1S (b) = 0 V; Tamb = 25 C f (MHz) 400 800 F MIN (dB) 1.1 1.2 GAMMA OPT (ratio) 0.719 0.628 (deg) 16.16 32.7 Rn () 31.18 29.74
DYNAMIC CHARACTERISTICS AMPLIFIER b Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA SYMBOL yfs Cig1-ss Cig2-ss Coss Crss Gtr PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance power gain Tj = 25 C f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BS(opt); GL = 0.5 mS; BL = BL(opt); note 1 f = 400 MHz; GS = 2 mS; BS = BS(opt); GL = 1 mS; BL = BL(opt); note 1 CONDITIONS MIN. 26 - - - - 30 27 TYP. 31 2.0 3.3 0.85 20 34 31 26 4 1.3 1.4 MAX. 40 2.5 - - - 38 35 30 - 1.9 2.1 UNIT mS pF pF pF fF dB dB dB dB dB dB
f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 22 GL = 1 mS; BL = BL(opt); note 1 NF noise figure f = 10.7 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS(opt) f = 800 MHz; YS = YS(opt) - - -
2003 Sep 30
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Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
SYMBOL Xmod
PARAMETER cross-modulation
CONDITIONS input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 10 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2
MIN. 90 - 100
TYP. - 92 105
MAX. - - -
UNIT dBV dBV dBV
Notes 1. For the MOS-FET not in use: VG1-S (a) = 0; VDS (a) = 0. 2. Measured in test circuit Fig.30. GRAPHS FOR AMPLIFIER b
handbook, halfpage
20
MGX445
(3) (2) (1)
ID (mA) 15
(4)
handbook, halfpage
(5)
24
MGX446
ID (mA) 16
(6)
(1)
(2)
(3) (4) (5) (6)
10
8 5
(7)
(7)
0 0 0.4 0.8 1.2 2 1.6 VG1-S (V)
0 0 2 4 6 8 10 VDS (V)
(1) (2) (3) (4)
VG2-S = 4 V. VG2-S = 3.5 V. VG2-S = 3 V. VG2-S = 2.5 V.
(5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V.
(1) VG1-S (b) = 1.4 V. (2) VG1-S (b) = 1.3 V. (3) VG1-S (b) = 1.2 V. (4) VG1-S (b) = 1.1 V.
(5) VG1-S (b) = 1 V. (6) VG1-S (b) = 0.9 V. (7) VG1-S (b) = 0.8 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
Fig.18 Transfer characteristics; typical values; amplifier b.
Fig.19 Output characteristics; typical values; amplifier b.
2003 Sep 30
13
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
60
MGX447
(2) (1)
(3) (4)
handbook, halfpage
40
MGX448
IG1 (A) 40
yfs (mS) 30
(5)
(1)
(2)
(3) (4)
20
20
(6)
10
(5) (7)
0 0 0.4 0.8 1.2 1.6 VG1-S (V) 2
0 0 4 8 12 16 20 ID (mA)
(1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V.
(5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V.
(1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V.
(4) VG2-S = 2.5 V. (5) VG2-S = 2 V.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
Fig.20 Gate 1 current as a function of gate 1 voltage; typical values; amplifier b.
Fig.21 Forward transfer admittance as a function of drain current; typical values; amplifier b.
2003 Sep 30
14
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
20
MGX449
ID (mA)
handbook, halfpage
16
MGX450
16
ID (mA) 12
12 8 8
4 4
0 0 10 20 30 40 50 IG1 (A)
0 0 1 2 3 4 5 VGG (V)
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.22 Drain current as a function of gate 1 current; typical values; amplifier b.
Fig.23 Drain current as a function of gate 1 supply voltage (VGG); typical values; amplifier b.
2003 Sep 30
15
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
20
MGX451
ID
(1) (2) (3)
handbook, halfpage
16
MGX452
(mA) 16
ID (mA) 12
(1) (2) (3) (4) (5)
(4)
12
(5) (6) (7) (8)
8
8
4
4
0 0 2 4 6 VGG = VDS (V)
0 0 2 4 VG2-S (V) 6
(1) RG1 (b) = 68 k. (2) RG1 (b) = 82 k. (3) RG1 (b) = 100 k. (4) RG1 (b) = 120 k.
(5) RG1 (b) = 150 k. (6) RG1 (b) = 180 k. (7) RG1 (b) = 220 k. (8) RG1 (b) = 270 k.
(1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V.
(4) VGG = 3.5 V. (5) VGG = 3.0 V.
VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.24 Drain current as a function of gate 1 (VGG) and drain supply voltage; typical values; amplifier b.
Fig.25 Drain current as a function of gate 2 voltage; typical values; amplifier b.
2003 Sep 30
16
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
30
MGX453
handbook, halfpage
(1) (2)
120
MGX454
IG1 (A) 20
Vunw (dBV) 110
(3) (4)
100
(5)
10 90
0 0 2 4 VG2-S (V) 6
80 0 20 40 60 gain reduction (dB)
(1) VGG = 5.0 V. (2) VGG = 4.5 V. (3) VGG = 4.0 V.
(4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); fw = 50 MHz; funw = 60 MHz; Tamb = 25 C; see Fig.30.
VDS (b) = 5 V; VDS (a) = VG1-S (a) = 0 V; Tj = 25 C; RG1 (b) = 150 k (connected to VGG); see Fig.4.
Fig.26 Gate 1 current as a function of gate 2 voltage; typical values; amplifier b.
Fig.27 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier b.
2003 Sep 30
17
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, halfpage
0
MGX455
handbook, halfpage
16
MGX456
gain reduction (dB) 20
ID (mA) 12
8
40 4
60 0 1 2 3 VAGC (V) 4
0 0 20 40 60 gain reduction (dB)
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Fig.30.
VDS (b) = 5 V; VGG = 5 V; VDS (a) = VG1-S (a) = 0 V; RG1 (b) = 150 k (connected to VGG); f = 50 MHz; Tamb = 25 C; see Fig.30.
Fig.28 Typical gain reduction as a function of AGC voltage; amplifier b.
Fig.29 Drain current as a function of gain reduction; typical values; amplifier b.
2003 Sep 30
18
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
handbook, full pagewidth
VAGC
VDS(a) 5V 4.7 nF
10 k 4.7 nF 50 4.7 nF g1 (a) d (a)
L1 2.2 H
g2
BF1205
s
4.7 nF RGEN 50 Vi 50
g1 (b)
d (b) L2 2.2 H RL 50
R G1 150 k
4.7 nF VGG 5V VDS(b) 5V
MDB813
Fig.30 Cross-modulation test set-up for amplifier b.
102 handbook, halfpage yis (mS) 10
MGX457
102 handbook, halfpage
MGX458
-102
| yfs | (mS) | yfs |
fs (deg)
10 b is fs
-10
1
10-1 10
g is 102 f (MHz) 103
1 10
102
f (MHz)
-1 103
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; ID (b)= 12 mA.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA.
Fig.31 Input admittance as a function of frequency; typical values; amplifier b.
Fig.32 Forward transfer admittance and phase as a function of frequency; typical values; amplifier b.
2003 Sep 30
19
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
BF1205
103 handbook, halfpage
MGX459
-103 rs (deg)
handbook, halfpage
10
MGX460
| yrs|
(S) 102 rs
yos (mS) 1 bos
-102
10
| yrs|
-10
10-1
gos
1 10
102
f (MHz)
-1 103
10-2 10
102
f (MHz)
103
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA.
Fig.33 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier b.
VDS (b) = 5 V; VG2-S = 4 V; VDS (a) = VG1-S (a) = 0 V; ID (b) = 12 mA.
Fig.34 Output admittance as a function of frequency; typical values; amplifier b.
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20
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
Scattering parameters: amplifier b VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 C f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 s11 MAGNITUDE (ratio) 0.987 0.985 0.978 0.968 0.956 0.941 0.924 0.905 0.884 0.861 0.837 ANGLE (deg) -3.76 -7.38 -14.63 -21.82 -28.92 -35.99 -42.93 -49.89 -56.57 -63.36 -70.05 s21 MAGNITUDE (ratio) 3.12 3.11 3.09 3.06 3.01 2.95 2.89 2.83 2.75 2.67 2.59 ANGLE (deg) 175.87 171.77 163.72 155.67 147.79 139.86 132.06 124.31 116.69 108.97 101.39 s12 MAGNITUDE (ratio) 0.00071 0.00136 0.00272 0.00396 0.00509 0.00616 0.00710 0.00791 0.00848 0.00900 0.00941 ANGLE (deg) 85.43 86.06 84.25 82.63 81.35 79.46 78.57 77.88 76.72 76.55 76.67
BF1205
s22 MAGNITUDE (ratio) 0.991 0.989 0.988 0.986 0.983 0.973 0.975 0.972 0.968 0.964 0.959 ANGLE (deg) -1.56 -3.11 -6.16 -9.17 -12.17 -15.16 -18.15 -21.07 -24.08 -27.03 -30.02
Noise data VDS (b) = 5 V; VG2-S = 4 V; ID (b) = 12 mA; VDS (a) = 0 V; VG1-S (a) = 0 V; Tamb = 25 C f (MHz) 400 800 F MIN (dB) (ratio) 1.3 1.4 0.662 0.578 F MIN (dB) (deg) 16.76 33.97 31.55 30.53 Rn ()
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21
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
PACKAGE OUTLINE Plastic surface mounted package; 6 leads
BF1205
SOT363
D
B
E
A
X
y
HE
vMA
6
5
4
Q
pin 1 index
A
A1
1
e1 e
2
bp
3
wM B detail X Lp
c
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT363
REFERENCES IEC JEDEC EIAJ SC-88
EUROPEAN PROJECTION
ISSUE DATE 97-02-28
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22
Philips Semiconductors
Product specification
Dual N-channel dual gate MOS-FET
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
BF1205
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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23
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R77/01/pp24
Date of release: 2003
Sep 30
Document order number:
9397 750 11784

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